![]() ![]() Neither condition in your two if statements require parenthesis. VHDL has fixed precedence with multiple operators of the same precedence. You could also note that the condition in an if statement is a boolean_expression (returns a boolean value), and expressions only require enclosing in matching left and right parenthesis to control association and evaluation order. Line 25 and 27 both assign a string value to std_logic type when the should assign an enumeration value (a character type). Line 18 makes the same mistake equality testing ck="1" while ck should also be the declared clock clk. String values are associated with string based types such as std_logic_vector, for example Line 17 `d<="000". areset is declared as std_logic, which uses enumeration values that are character literals. The first error on Line 16 occurs because there is no declared equality operator that compares between std_logic and string. ![]() Ghdl -a -ieee=synopsys -fexplicit acircuit.vhdlĪcircuit.vhdl:16:18: no function declarations for operator "="Īcircuit.vhdl:18:15: no declaration for "ck"Īcircuit.vhdl:25:12: can't match string literal "001" with type enumeration subtype "std_logic"Īcircuit.vhdl:27:12: can't match string literal "000" with type enumeration subtype "std_logic"ĥ port(a:in std_logic_vector(2 downto 0) ġ0 architecture ACircuitoComparatore of CircuitoComparatore isġ1 signal c,d: std_logic_vector(2 downto 0) Analyzing your design specification unchanged:
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |